-- TotoOppus - 13 Jun 2008

EcE? 201 Advanced Digital Design

Course Description Advanced Digital System Design covers mastery of combinatorial logic, sequential system, algorithmic state machine and hardware description language (HDL). This course covers hardware programming language – specifically VERILOG.

Course Objectives

  • To gain mastery of combinatorial logic, sequential system, algorithmic state machine and
  • To have a hands-on knowledge of FPGA and VERILOG HDL and its applications.
Course Topics
  • Introduction to FPGA
  • Introduction to hardware programming languages (VERILOG)
  • Behavioral modeling using HDL
  • Sequential processing using HDL
  • HDL synthesis
  • HDL Case Studies and Applications
  • FPGA Applications
  • CE 40/Elc 111, Digital Design or equivalent
Lecture Text
  • Michael Ciletti, Modelling, Synthesis, and Rapid Prototyping with the Verilog HDL, Prentice Hall New Jersey 1999.
References *Course Requirements and Grading System *
  • Class Work 90% (2 long tests, quizzes, 5-7 programming assignments)
  • Class participation 10% (class conduct, recitation, board work, assignments and problem sets)

  • 92 and up A
  • 87 to 91+ B+
  • 81 to 86+ B
  • 76 to 80+ C+
  • 70 to 75+ C
  • 60 to 69+ D
  • 59+ and below F
Class Policies
  • Class attendance is always checked (by the beadle).
  • Students are allowed 3 cuts. Exceeding the allowable number of cuts automatically merits a grade of W for the course.
  • Maintain an atmosphere of an academic classroom.
Mailing List
  • A mailing list (or e-group) shall be established for the course. Various materials may be distributed thru the mailing list. While membership in the mailing list is not a requirement of the course, students who do not join the mailing list are responsible for material(s) distributed thru the mailing list.
Topic revision: r3 - 11 Jun 2010 - 07:10:09 - TotoOppus
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